Analog decoders for high rate convolutional codes

Abstract

Recently, several VLSI implementations of analog decoders have been reported for rate 1/2 tailbiting convolutional codes. The main advantages of analog decoders are much higher decoding speed, smaller chip size and lower power consumption when compared to an equivalent digital decoder. Since many high speed applications require code rates well above 1/2 we focus on high rate tailbiting convolutional codes. For digital decoder implementations it has been shown by C. Weiss and J. Berkmann (see Proc. 3rd ITG Conf. Source and Channel Coding, Munich, Germany, p.199-207, Jan. 2000) that it is advantageous to use the trellis of the dual code which is less complex for high rate codes. The novel analog decoder design proposed in this paper can be seen as a direct analog implementation of the algorithm described by Weiss and Berkman.