Linear arrays for residue mappers

Abstract

Pipelined structures based on the residue number system (RNS) have been found suitable for high-speed arithmetic. The polynomial RNS (PRNS) can speed up digital signal processing (DSP)-related tasks like correlations and convolutions. The authors introduce pipelined arrays able to serve as mapping modules for PRNS-based functional units. Such mappings, involve polynomial evaluation coupled with modulo operations. The authors show how VLSI array processors can perform modulo operations in a parallel environment. A methodology is presented by which the reliability of such fast architectures can be ensured simply by probing into the mechanics of the computations involved. The proposed techniques provide a hardware base for PRNS implementations. At the same time, a reasonable degree of fault-tolerance can be guaranteed in the face of high system throughputs.<>