Fast Design-Space Exploration Method for SW/HW Codesign on FPGAs

Yuki Ando, S. Shibata, S. Honda, H. Tomiyama, H. Takada
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Abstract

This paper presents an efficient design-space exploration method to identify the Pareto solution for the relation between the execution time and the hardware area. Initially, our method takes a particular system mapping that is surely in the Pareto solution, and then repeats the local search and the update of the Pareto solution until the Pareto solution reaches a steady state. Compared to genetic-algorithm-based methods, we found that our method outputs the Pareto solution with a smaller number of explorations for larger design spaces.
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fpga软件/硬件协同设计的快速设计空间探索方法
针对执行时间与硬件面积之间的关系,提出了一种有效的设计空间探索方法来识别Pareto解。首先,我们的方法采用一个特定的系统映射,它肯定在帕累托解中,然后重复局部搜索和更新帕累托解,直到帕累托解达到稳定状态。与基于遗传算法的方法相比,我们发现我们的方法在更大的设计空间中以更少的探索次数输出帕累托解。
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