The shared cache reconfigurable method for low power on CMPs

Abstract

As the multi-core technology develops, the cache size becomes larger in CMP(Chip Multi-core Processors), which is attended as the main factor in power consumption. How to reduce the power consumption with no influence on the microprocessor performance is an important problem to the cache design. This paper researches the related technology about cache low power and proposes a shared cache reconfigurable method in CMP for low power. First, this paper analyses the cache reconfiguration necessity by the static reconfiguration. Then add reconfigurable strategy during cache access. In the end, we gives the experiment result that the method can save energy consumption, while the performance decline is little.