Universal Resonator Control ASIC for Low C- SWaP INS

A. Challoner, R. Chueng, V. Veselý, Peter Bond, K. Armstrong, David Hayner, E. Wittinger, Anjelica Pazmino
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Abstract

A novel Universal Resonator Controller (URC) architecture and ASIC design is presented for precision, wideband resonator velocity control and the digitally demodulated readout of resonator velocity and frequency with the designed resolution «100ppb/rt-Hz), linearity (lppm) and sensor bandwidth (>100Hz) required for navigation grade vibratory inertial sensors. In this paper, our two-channel URC ASIC design is described for control and readout of the two inertially-coupled modes of a vibratory gyroscope or the two uncoupled modes of a dual beam vibratory accelerometer. Like the evolution of the high yield, high performance operational amplifier, single, dual, or quad channel URC ASIC configurations are anticipated to implement single-axis, two-axis, or three-axis IMU or INS. Our first URC ASIC has been submitted for fabrication in a 4.1mmx4.1mm, 180nm CMOS die. Each URC additionally provides digitally selectable analog gains and two DACs per channel with up to 30V range for tuning of residual machining errors, on-line precision quadrature or amplitude control. A low power digital demodulator is being developed with FPGA for subsequent CMOS integration. With this universal ASIC architecture and exemplary wafer-level-packaged, high Q MEMS in-plane resonators, a compact 2D and 3D Navigation System on Chip (NSoC™) architecture is enabled to increase the production scale and radically reduce the cost, size, weight, and power of electronics and systems for numerous existing and future highly compact MEMS inertial navigation applications. The ASIC design and its application to CVG and DRBA control, will be discussed including the electronics trades, and analog breadboard developments supporting its design.
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用于低碳交换INS的通用谐振器控制ASIC
提出了一种新型的通用谐振器控制器(URC)架构和ASIC设计,用于精确,宽带谐振器速度控制以及谐振器速度和频率的数字解调读出,设计分辨率为100ppb/rt-Hz),线性度(lppm)和传感器带宽(>100Hz),用于导航级振动惯性传感器。本文描述了用于控制和读出振动陀螺仪的两个惯性耦合模式或双光束振动加速度计的两个非耦合模式的双通道URC ASIC设计。与高产量、高性能运算放大器的发展一样,单通道、双通道或四通道URC ASIC配置有望实现单轴、两轴或三轴IMU或INS。我们的第一个URC ASIC已经提交在4.1mmx4.1mm, 180nm CMOS芯片上制造。每个URC还提供数字可选的模拟增益和每个通道两个dac,最高可达30V范围,用于调谐残余加工误差,在线精密正交或幅度控制。利用FPGA开发了一种低功耗数字解调器,用于后续CMOS集成。凭借这种通用ASIC架构和典型的晶圆级封装的高Q MEMS平面内谐振器,紧凑的2D和3D导航系统芯片(NSoC™)架构能够增加生产规模,并从根本上降低许多现有和未来高度紧凑的MEMS惯性导航应用的电子和系统的成本、尺寸、重量和功率。将讨论ASIC设计及其在CVG和DRBA控制中的应用,包括电子贸易,以及支持其设计的模拟面包板开发。
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