A Merged Synthesis Technique for Fast Arithmetic Blocks Involving Sum-of-Products and Shifters

Abstract

In modern digital signal processing (DSP) and graphics applications, the arithmetic sum-of-products, shifters and adders are important modules, contributing a significant amount to the overall delay of the system. A datapath structure consisting of multiple arithmetic sum-of-product, shifter and adder blocks is often found in the timing-critical path of the chip. In this paper, we propose a new operator-level merging technique to synthesize this type of datapath structure. In our approach, we combine the shifting operation with the partial product reduction stage of the sum-of-product blocks. This enables us to implement the functionality of the original design by using only one carry- propagate adder block (instead of two carry-propagate adders). As a result, the timing-critical path of the design gets shortened by a significant percentage and the overall performance of the design improves. Our experimental data shows that the datapath block generated by our approach is significantly faster (13.28% on average) with a modest area penalty (3.24% on average) than the corresponding block generated by a commercially available best-in-class datapath synthesis tool. These improvements were verified on placed-and-routed designs as well.