Sudhir K. Satpathy, S. Mathew, Jiangtao Li, Patrick Koeberl, M. Anders, Himanshu Kaul, Gregory K. Chen, A. Agarwal, S. Hsu, R. Krishnamurthy
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引用次数: 26
Abstract
A 250K probing-resilient PUF array with measured 2GHz operation and total energy consumption of 13fJ/bit at 0.9V, 25°C is fabricated in 22nm tri-gate CMOS. Hybrid PUF circuit with integrated load modulation and run-time soft dark-bit mask generation enables identification of unstable PUF bits with 100% accuracy, eliminating the need for multiple voltage/temperature characterization while also reducing bit-error down to 1.94%. Transient behavior of the hybrid PUF cell, along with the use of balanced local clock routing improves resiliency to invasive power-up probing attacks by 75%.