Scheduling for an Embedded Architecture with a Flexible Datapath

Abstract

Embedded systems put stringent demands on post-fabrication  flexibility as well as computing performance efficiency. The FlexSoC  scheme approaches the implementation of embedded systems from a  general-purpose processor point of view: The FlexCore processor has  a datapath whose configuration is under instruction control; in  its minimal configuration, the processor represents a simple 5-stage  pipeline. However, thanks to a flexible processor interconnect, the  FlexCore datapath configuration can be changed at run-time to boost  performance for the currently executed code. The consequence of this  flexibility is that pipelining is not hard-coded into the datapath,  but all instruction scheduling needs to be done by software at  compile time. We present a scheduling technique for the FlexCore  processor allowing for efficient use of datapath resources over a  flexible interconnect. The flexible interconnect indeed offers  plenty of opportunities for parallel operations, but it also makes  the analysis of instruction dependencies difficult. Thus, we propose  to use a SAT-solver to enable the scheduler to efficiently check  constraints on computing and communication resources. In an  evaluation on four different benchmarks, our scheduler is shown to  produce schedules that are as efficient as fine-tuned, manual  schedules.