Performance comparison of 8 bit & 32 bit logarithmic barrel shifter using Fredkin & SCRL gates

Abstract

Barrel shifters perform the shifting functions and are used in floating point arithmetic operations. The logarithmic barrel shifter designed using Fredkin and Feynman reversible gates result in lesser power consumption but there is a considerable increase in path delay, garbage outputs and ancilla inputs which reduces the performance efficiency. This paper presents an implementation of 8 bit and 32 bit logarithmic barrel shifter using SCRL(super conservative reversible logic) and also fredkin gates and a performance comparison is made in terms of garbage outputs, ancilla inputs, power consumption and path delay. The behavioural simulation is checked using verilog language and implementation is done on Xilinx 13.1 tool to find the power consumption. The implemented design with SCRL gate shows lesser garbage outputs, ancilla inputs and path delay.