W. Kuzmicz, E. Piwowarska, A. Pfitzner, D. Kasprowicz
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引用次数: 19
Abstract
Static power consumption due to excessive leakage currents is a major problem in CMOS digital ICs with gate lengths of 90 nm and below. In this paper the physics and modelling of these currents is discussed, with special emphasis on variability and its effect on the statistical spread of the static power consumption and total power consumption.
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