High Throughput Hardware Implementation of Secure Hash Algorithm (SHA-3) Finalist: BLAKE

Abstract

Cryptographic hash functions are at heart of many information security applications like digital signatures, message authentication codes (MACs), and other forms of authentication. In consequence of recent innovations in cryptanalysis of commonly used hash algorithms, NIST USA announced a publicly open competition for selection of new standard Secure Hash Algorithm called SHA-3. An essential part of this contest is hardware performance evaluation of the candidates. In this work we present a high throughput efficient hardware implementation of one of the final round candidate of SHA-3: BLAKE. We implemented and investigated the performance of BLAKE on latest Xilinx FPGAs. We show our results in form of chip area consumption, throughput and throughput per area. We compare and contrasted these results with most recently reported implementations of BLAKE. Our design ranked highest in terms of speed, achieving throughputs of 2.47Gbps on Virtex 7 and 2.28Gbps on Virtex 5.