Implementation of 32-bit RISC processors without interlocked Pipelining on Artix-7 FPGA board

Abstract

RISC processors have wide range of applications depending on speed and power consumption. Here a design of low power RISC processor is proposed using forwarding and stalling process. Using suitable clocking methodology speed can also be enhanced. A design of 5 stage pipelining architecture with hazard and forwarding unit for pipeline control is presented. Fetch, Decode, Execute, Memory and Write back are the 5 stages. A single edge trigger clock is used for intermediate stages. The RISC processor is designed based on MIPS instruction set. A non-interlocked pipelining technique is used. Power reduction of up to .09W was achieved using above mentioned techniques. The design is implemented on Artix-7 FPGA using Xilinx Vivado.