Design and FPGA implementation of iterative decoders for codes on graphs

Abstract

This work presents a Field Programmable Gate Array (FPGA) implementation of the Min-Sum iterative decoding algorithm for the (8,4) extended Hamming code using a reconfigurable computing system. The Mitrion-C high level language (HLL) is used to program the FPGAs, since it provides flexible tools for FPGA-based prototyping and functional verification for hardware design. A hardware-efficient implementation of the Min-step in the Min-Sum decoder, which eliminates the use of floating point multipliers, is also presented. The parallelism offered by the Min-Sum algorithm is exploited in hardware, resulting in a 15 fold speedup over optimized software implementations. The performance of the hardware implementation is virtually the same as that predicted by computer simulations, validating the hardware design.