Performance improvement using two level branch predictor on the mobile processor

Abstract

In the last few years, the microprocessor of mobile device has been developed into multi-core, multi-issue, and deep pipeline for high-performance. But maximizing the parallelism of a pipeline and deepening pipeline cause more penalties so that branch predictor is more and more important. One of the efficient ways to improve its performance is generally to increase the size of the branch predictor. However, increasing the size of branch predictor necessarily involves the increase of memory indexing time and power consumption. Therefore, to improve the performance of branch predictor considering the mobile environment, we have studied the effect on performance improvement by changing the other factors while remaining the size of the memory fixed with 2-level branch predictor. We experimented to investigate the performance improvement by modifying the associativity of Branch Target Buffer (BTB) and the size of Branch History Register (BHR). The simulation was performed using SimpleScalar 3.0 based on ARM Cortex-A15 and benchmarks from SPEC CPU2000. As a result, in the 2-level branch predictor structure, when reducing the length of BHR in 8 bit, the increase of Instruction Per Cycle (IPC) is the highest as 0.599%. Therefore, we concluded that to modify the length of BHR of branch predictor is most effective way to improve the performance of the processor.