A Low Power Hard Decision Decoder for BCH Codes

Abstract

In decoding of Bose-Chaudhuri-Hocquenghem codes, Peterson’s algorithm is more efficient for codes with single, double and triple error correcting capabilities. Numerous methods were proposed to reduce the hardware complexity caused due to the inversion operation involved in the Peterson’s algorithm. In this paper, a low complex hardware BCH decoder using inversion-less Peterson’s algorithm presented in literature is designed and its performance is verified with the Matlab results. An attempt is made to design a low power version of this low complex BCH decoder by replacing the parallel Chien search architecture in the decoder with the two-step p-parallel Chien search approach that is originally used in literature with the Berlekamp-Massey Algorithm. For use with the inversion-less Peterson’s algorithm the parallel Chien search architecture has been modified and the resultant decoder has shown a power reduction of up to 42 percentage with a moderate increase in area by 10 percentage.