D. Yakimets, T. H. Bao, M. Bardon, M. Dehan, N. Collaert, A. Mercha, Z. Tokei, A. Thean, D. Verkest, K. De Meyer
{"title":"Lateral versus vertical gate-all-around FETs for beyond 7nm technologies","authors":"D. Yakimets, T. H. Bao, M. Bardon, M. Dehan, N. Collaert, A. Mercha, Z. Tokei, A. Thean, D. Verkest, K. De Meyer","doi":"10.1109/DRC.2014.6872333","DOIUrl":null,"url":null,"abstract":"Nominal LG VFET-based RO may operate up to ~60% faster than LFET-based RO at the same energy per switch for both 7nm and 5nm technology nodes depending on the layout and BEOL-load. With VFETs, relaxing the LG is possible and it results in an extra 27% in IEFF in comparison to the nominal LG case. In addition, VFETs enable different layouts, which can be used to optimize performance under certain BEOL-load. Introduction of VFETs is more favorable at the 5nm node than at the 7nm node. As such, VFETs show a performance competitive path for continued scaling beyond 7nm technologies.","PeriodicalId":293780,"journal":{"name":"72nd Device Research Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2014-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"15","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"72nd Device Research Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/DRC.2014.6872333","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 15
Abstract
Nominal LG VFET-based RO may operate up to ~60% faster than LFET-based RO at the same energy per switch for both 7nm and 5nm technology nodes depending on the layout and BEOL-load. With VFETs, relaxing the LG is possible and it results in an extra 27% in IEFF in comparison to the nominal LG case. In addition, VFETs enable different layouts, which can be used to optimize performance under certain BEOL-load. Introduction of VFETs is more favorable at the 5nm node than at the 7nm node. As such, VFETs show a performance competitive path for continued scaling beyond 7nm technologies.
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