{"title":"4×2Gbps Source-Synchronous Transmitter in 45nm CMOS","authors":"Anant S. Kamath, Vikas Sinha, Sujoy Chakravarty","doi":"10.1109/VLSID.2011.33","DOIUrl":null,"url":null,"abstract":"A 4-lane, 2Gbps-per-lane, source synchronous, voltage-mode differential transmitter is presented here. Staggered switching of driver termination is used to obtain controlled, nearlinear rise/fall transitions on the pads. The timing for the staggering is generated by a calibrated digitally controlled delay line. An on-chip high bandwidth regulator serves as a low impedance 400mV source required for voltage mode transmission. The transmitter, designed and fabricated in 45nm CMOS technology, occupies a core area of 0.013mm2 per lane and consumes 4.3mW/Gbps.","PeriodicalId":371062,"journal":{"name":"2011 24th Internatioal Conference on VLSI Design","volume":"12 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2011-01-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2011 24th Internatioal Conference on VLSI Design","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSID.2011.33","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
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Abstract
A 4-lane, 2Gbps-per-lane, source synchronous, voltage-mode differential transmitter is presented here. Staggered switching of driver termination is used to obtain controlled, nearlinear rise/fall transitions on the pads. The timing for the staggering is generated by a calibrated digitally controlled delay line. An on-chip high bandwidth regulator serves as a low impedance 400mV source required for voltage mode transmission. The transmitter, designed and fabricated in 45nm CMOS technology, occupies a core area of 0.013mm2 per lane and consumes 4.3mW/Gbps.
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