{"title":"Parallel architectures: Techniques for compiler-directed cache coherence","authors":"L. Choi, Hock-Beng Lim, P. Yew","doi":"10.1109/M-PDT.1996.544438","DOIUrl":null,"url":null,"abstract":"Compiler-directed cache coherence can help close the gap between processor and memory speed. The authors explain the concepts underlying techniques and survey various approaches to this strategy.","PeriodicalId":325213,"journal":{"name":"IEEE Parallel & Distributed Technology: Systems & Applications","volume":"11 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1996-01-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Parallel & Distributed Technology: Systems & Applications","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/M-PDT.1996.544438","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 4
Abstract
Compiler-directed cache coherence can help close the gap between processor and memory speed. The authors explain the concepts underlying techniques and survey various approaches to this strategy.
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