An integrated low jitter PLL for high speed high resolution DACs

Abstract

This paper presents a high performance low jitter PLL. Fully differential PFD and divider are implemented to minimize its in-band noise and to achieve high common mode and power supply noise rejection. A low jitter LC-tank VCO is used to achieve low out-of-band noise. A level shifter is inserted between the LF and VCO to optimize the VCO performance. The PLL is fabricated in SMIC 65nm CMOS low leakage process. The operating frequency range of the VCO is 2–3GHz, and the rms period jitter of the PLL at 3GHz due to supply noise is 374fs with an additive 2MHz 50mVpp sinusoidal power supply noise. The PLL has been used as a clock multiplier for a 14bit 2.5GSPS high speed high resolution DAC.