A 180 nm efficient low power and optimized area ALU design using gate diffusion input technique

Abstract

Arithmetic and Logic block in processor is the most crucial and core component in CPU as well as number of Embedded and microprocessors. Power consumption and area are also main traits in ALU. Usually ALU is combinations of blocks which performs logical and arithmetical operations and are realized using circuits in combinational form. This paper depicts the major focus on to minimize the power consumption and reduce area by taking advantage of using GDI technique i. e. gate diffusion input technique. By using GDI technique the 4∗1multiplexer, 2∗1multiplexer as well as full adder are design. The simulation is performed by using Tanner ED tool in 180 nm technology and the results are compared with conventional pass transistor and CMOS logic. Using GDI technique the overall performance and efficiency of circuit also boost.