Design of 4-bit serial-parallel multiplier in Quantum-Dot Cellular Automata

Abstract

Quantum-Dot Cellular Automata (QCA) as technology is a promising candidate that has tremendous potential to replace CMOS due to its outstanding features such as low-power, extremely high density, fast operation speed. However, due to its four-phased clocking scheme and timing requirements, various issues in timing for interconnections and feedback are present. In this paper, the delay transfers and retiming using QCA characteristics to solve timing issues has been explored. The problem in assigning appropriate clock zones and feedback has been addressed. Based on the design rules and constraints, retiming technique has been discussed to perform delay-transfer and time-scaling to achieve efficient clock zone assignment. A serial adder has been designed that uses multilayer crossover. As a case study, a 4-bit serial-parallel multiplier has been designed using the serial adder as basic input circuit to illustrate the rules of retiming.