Rigorous Development of Embedded Systems Supported by Formal Tools

Abstract

A rigorous approach to development of embedded systems is proposed in the paper. The concept is based on introduction of formal modeling branch in parallel to the classical V-development method. SysML is used for description of the developed components, and then these artifacts are translated into Colored Petri Nets (CPN) blocks. The correctness of the CPN models is described using temporal logic and finally verified using model checking tools. The proposed concept enables detection of structural errors in early development stages. The paper describes the next steps of research in this area. Translations of remaining SysML diagrams are included, and the modeling-verification chain is described.