An efficient fixed width multiplier for digital filter

Abstract

We implement a high speed and low power FIR digital filter design using the fixed width booth multiplier. To reduce the truncation error in fixed width multiplier Adaptive Conditional Probability Estimator is used (ACPE). To achieve higher speed, the modified Booth encoding has been used and also to speed up the addition the carry look ahead adder is used as a carry propagate adder. The multiplier circuit is designed using VERILOG and synthesized using Xilinx ISE9.2i simulator. The area, power and delay of the designed filter is analysed using cadence tool.