{"title":"A new recessed gate MOSFET structure with the graded source/drain","authors":"Woo-Hyeong Lee, Young-June Park, J. Lee","doi":"10.1109/DRC.1993.1009567","DOIUrl":null,"url":null,"abstract":"Summary form only given. A gate recessed MOS (GR-MOS) structure with the selectively halo-doped channel by boron implantation carried out after graded (source/drain) (S/D) formation is proposed. The S/D is formed without n/sup +/ counter-doping to the channel doping. Initial characterization results of GR-MOSFETs having a 0.25 mu m channel length are presented in comparison with the conventional lightly doped drain (LDD)-MOSFETs. It was verified that the new concept gives improved device characteristics over the LDD structure for a wide range of bias conditions and channel lengths, and renders the device design window wider in deep submicron devices. >","PeriodicalId":310841,"journal":{"name":"51st Annual Device Research Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1993-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"51st Annual Device Research Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/DRC.1993.1009567","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2
Abstract
Summary form only given. A gate recessed MOS (GR-MOS) structure with the selectively halo-doped channel by boron implantation carried out after graded (source/drain) (S/D) formation is proposed. The S/D is formed without n/sup +/ counter-doping to the channel doping. Initial characterization results of GR-MOSFETs having a 0.25 mu m channel length are presented in comparison with the conventional lightly doped drain (LDD)-MOSFETs. It was verified that the new concept gives improved device characteristics over the LDD structure for a wide range of bias conditions and channel lengths, and renders the device design window wider in deep submicron devices. >
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