Evaluating the scalability and performance of 3D stacked reconfigurable nanophotonic interconnects

2013 ACM/IEEE International Workshop on System Level Interconnect Prediction (SLIP) Pub Date : 2013-06-02 DOI:10.1109/SLIP.2013.6681676

R. Morris, Avinash Karanth Kodi, A. Louri

引用次数: 0

Abstract

As we integrate hundreds of cores in the future, energy-efficiency and scalability of Network-on-Chips (NoCs) has become a critical challenge. In order to achieve higher performance-per-Watt than traditional metallic interconnects, researchers are exploring alternate energy-effident emerging technology solutions. In this paper, we propose to combine two emerging technologies, namely 3D stacking and nanophotonics that can deliver high on-chip bandwidth and low energy/bit to achieve a high-throughput, reconfigurable and scalable NoC for many-core systems. Our simulation results indicate that the execution time can be reduced up to 25% and energy consumption reduced by 23% for Splash-2, PARSEC, SPEC CPU2006 and synthetic benchmarks for 64-core and 256-core versions.

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评价三维堆叠可重构纳米光子互连的可扩展性和性能

随着我们未来集成数百个核心，片上网络(noc)的能源效率和可扩展性已成为一个关键挑战。为了实现比传统金属互连更高的每瓦性能，研究人员正在探索替代节能新兴技术解决方案。在本文中，我们提出结合两种新兴技术，即3D堆叠和纳米光子学，可以提供高片上带宽和低能量/位，以实现多核系统的高吞吐量，可重构和可扩展的NoC。仿真结果表明，在64核和256核版本的Splash-2、PARSEC、SPEC CPU2006和综合基准测试中，执行时间最多可减少25%，能耗减少23%。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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2013 ACM/IEEE International Workshop on System Level Interconnect Prediction (SLIP)

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