Implementation of low power flash ADC by reducing comparators

Abstract

The need for a high speed and low power ADC is very essential for various applications. Flash ADCs are always the architecture choice where maximum sample rate and moderate resolution is needed. Even though flash ADC is the fastest type available it takes enormous amount of IC real estate to implement. The main disadvantage of flash ADC is that it need large area and dissipate large amount of power. To overcome this complexity number of comparators are reducing by using multiplexers. Here the multiplexers are used to generate reference voltages. A 4-bit CMOS based flash ADC is presenting, which uses reduced comparator and multiplexer based architecture. Here both the analog and the digital parts of the proposed ADC are completely modified. This architecture uses only 4 comparators for a 4 bit ADC. This 4-bit ADC is designed and simulated in Hspice with 1.2 V supply voltage.