Reduction of design complexity using virtual hardware platforms

Abstract

Summary form only given. Our work alms to accelerate FPGA application development by raising the level of abstraction and facilitating design reuse. We propose a solution based on network of nodes, communicating using a packet-based protocol. This network of nodes is known as customisable modular platform (CMP). A node is a computational unit, which can be hardware core running on an FPGA, or a thread running on a processor or a DSP. Hardware nodes can span over several FPGAs or there can be several nodes on a single FPGA. The packet-based communication protocol is implemented using an interchangeable interface. This interface provides a seamless data interchange between the nodes, independent of the implementation target architecture or abstraction. The communication packets of this protocol include control information and data, i.e. header and payload.