A New 6T SRAM Memory Cell Based on FINFET Process

Abstract

With the development of semiconductor process, CMOS circuit size continues to shrink and the bulk silicon process has been difficult to meet the performance and power requirements of devices and circuits. At the same time, FINFET process has sprung up and replaced planar MOSFET due to their superior performance, power efficiency and scalability. The paper attempts to design a 6T SRAM memory cell in which it change PG transistors from NMOS to PMOS based on FINFET process. The PMOS SRAM memory cell is beneficial to area, speed and power consumption because the same size of PMOS drive capability is close to or even exceeds NMOS. From the results of simulation, we can see that although our new design can improve read and write speed and write margin (WM), the read static-noise margin (RSNM) deteriorates in worse corners. Hence, it need read assist circuits to improve RSNM.