CUGR: Detailed-Routability-Driven 3D Global Routing with Probabilistic Resource Model

Jinwei Liu, Chak-Wa Pui, Fangzhou Wang, Evangeline F. Y. Young
{"title":"CUGR: Detailed-Routability-Driven 3D Global Routing with Probabilistic Resource Model","authors":"Jinwei Liu, Chak-Wa Pui, Fangzhou Wang, Evangeline F. Y. Young","doi":"10.1109/DAC18072.2020.9218646","DOIUrl":null,"url":null,"abstract":"Many competitive global routers adopt the technique of compressing the 3D routing space into 2D in order to handle today’s massive circuit scales. It has been shown as an effective way to shorten the routing time, however, quality will inevitably be sacrificed to different extents. In this paper, we propose two routing techniques that directly operate on the 3D routing space and can maximally utilize the 3D structure of a grid graph. The first technique is called 3D pattern routing, by which we combine pattern routing and layer assignment, and we are able to produce optimal solutions with respect to the patterns under consideration in terms of a cost function in wire length and routability. The second technique is called multi-level 3D maze routing. Two levels of maze routing with different cost functions and objectives are designed to maximize the routability and to search for the minimum cost path efficiently. Besides, we also designed a cost function that is sensitive to resources changes and a post-processing technique called patching that gives the detailed router more flexibility in escaping congested regions. Finally, the experimental results show that our global router outperforms all the contestants in the ICCAD’19 global routing contest.","PeriodicalId":428807,"journal":{"name":"2020 57th ACM/IEEE Design Automation Conference (DAC)","volume":"s3-44 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2020-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"36","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2020 57th ACM/IEEE Design Automation Conference (DAC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/DAC18072.2020.9218646","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 36

Abstract

Many competitive global routers adopt the technique of compressing the 3D routing space into 2D in order to handle today’s massive circuit scales. It has been shown as an effective way to shorten the routing time, however, quality will inevitably be sacrificed to different extents. In this paper, we propose two routing techniques that directly operate on the 3D routing space and can maximally utilize the 3D structure of a grid graph. The first technique is called 3D pattern routing, by which we combine pattern routing and layer assignment, and we are able to produce optimal solutions with respect to the patterns under consideration in terms of a cost function in wire length and routability. The second technique is called multi-level 3D maze routing. Two levels of maze routing with different cost functions and objectives are designed to maximize the routability and to search for the minimum cost path efficiently. Besides, we also designed a cost function that is sensitive to resources changes and a post-processing technique called patching that gives the detailed router more flexibility in escaping congested regions. Finally, the experimental results show that our global router outperforms all the contestants in the ICCAD’19 global routing contest.
查看原文
分享 分享
微信好友 朋友圈 QQ好友 复制链接
本刊更多论文
基于概率资源模型的详细可达性驱动的三维全局路由
许多竞争激烈的全球路由器采用将3D路由空间压缩为2D的技术,以处理当今庞大的电路规模。实践证明,这是一种有效的缩短布线时间的方法,但不可避免地会在一定程度上牺牲质量。在本文中,我们提出了两种直接操作三维路由空间的路由技术,可以最大限度地利用网格图的三维结构。第一种技术被称为3D模式路由,通过该技术,我们将模式路由和层分配结合起来,并且我们能够根据线长度和可达性的成本函数产生关于所考虑的模式的最优解决方案。第二种技术被称为多层次3D迷宫路径。设计了具有不同代价函数和目标的两层迷宫路径,使可达性最大化,并有效地寻找代价最小的路径。此外,我们还设计了一个对资源变化敏感的代价函数和一种称为补丁的后处理技术,使详细路由器在逃离拥塞区域时具有更大的灵活性。最后,实验结果表明,我们的全局路由器在ICCAD ' 19全球路由竞赛中表现优异。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
求助全文
约1分钟内获得全文 去求助
来源期刊
自引率
0.00%
发文量
0
期刊最新文献
FCNNLib: An Efficient and Flexible Convolution Algorithm Library on FPGAs AXI HyperConnect: A Predictable, Hypervisor-level Interconnect for Hardware Accelerators in FPGA SoC Pythia: Intellectual Property Verification in Zero-Knowledge Reuse-trap: Re-purposing Cache Reuse Distance to Defend against Side Channel Leakage Navigator: Dynamic Multi-kernel Scheduling to Improve GPU Performance
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
0
微信
客服QQ
Book学术公众号 扫码关注我们
反馈
×
意见反馈
请填写您的意见或建议
请填写您的手机或邮箱
已复制链接
已复制链接
快去分享给好友吧!
我知道了
×
扫码分享
扫码分享
Book学术官方微信
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术
文献互助 智能选刊 最新文献 互助须知 联系我们:info@booksci.cn
Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。
Copyright © 2023 Book学术 All rights reserved.
ghs 京公网安备 11010802042870号 京ICP备2023020795号-1