{"title":"A 3.4 GB/S Low Latency 1 Bit Input Digital FIR-Filter in 0.13 μM CMOS","authors":"H. Fredriksson, Christer Svensson, A. Alvandpour","doi":"10.1109/MIXDES.2007.4286146","DOIUrl":null,"url":null,"abstract":"This paper presents a low latency, one bit input, high-speed FIR-filter designed for multi-Gb/s mixed signal decision feedback equalizers. The filter utilizes a carry-save FIR tap structure and an efficient dual-edge-flip-flop-multiplexer. The filter has been implemented in a standard 0.13 μm CMOS technology. Simulation results from extracted layout shows correct functionality up to 3.4 G words/s with a latency ≪280 ps.","PeriodicalId":310187,"journal":{"name":"2007 14th International Conference on Mixed Design of Integrated Circuits and Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2007-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2007 14th International Conference on Mixed Design of Integrated Circuits and Systems","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/MIXDES.2007.4286146","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
Abstract
This paper presents a low latency, one bit input, high-speed FIR-filter designed for multi-Gb/s mixed signal decision feedback equalizers. The filter utilizes a carry-save FIR tap structure and an efficient dual-edge-flip-flop-multiplexer. The filter has been implemented in a standard 0.13 μm CMOS technology. Simulation results from extracted layout shows correct functionality up to 3.4 G words/s with a latency ≪280 ps.
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