Design of a high-throughput low-latency extended golay decoder

Abstract

In this paper, we propose a parallel architecture of the imperfect maximum likelihood decoding (IMLD) method, called PIMLD. It is further implemented onto an FPGA and applied to decode the (24,12,8) extended Golay code. Experimental results show that the proposed PIMLD decoder achieves 12.0 Gb/s throughput at 500 MHz frequency. Moreover, the latency for the decoder is only 5 clock cycles.