A Method of Gate-Level Circuit Reliability Estimation Based on Iterative PTM Model

Abstract

The rapid development of nanotechnology has opened up new possibilities and introduced new challenges for circuit design. It is very important to study new analysis methods for accurate circuit reliability. Few methods for evaluating circuit reliability were proposed in recent years. For example, the original probabilistic transfer matrix (PTM) model has large time and space overhead, so it can only calculate small scale circuits, the improved PTM model proposed in [2] can handle large scale circuits but it also has large time overhead. In this paper, the concept of macro-gate is defined and an iterative PTM model based on macro-gate is proposed. Based on this model, a circuit reliability evaluation algorithm that can calculate the circuit reliability from primary input to any level of the circuit is given. The complexity of the proposed algorithm related to the number of macro-gates contained in the circuit is linear. Experimental results show that the proposed method has the same accuracy as the PTM model, but it has lower time overhead for large circuits.