D. Knoll, B. Heinemann, R. Barth, K. Blum, J. Borngraber, J. Drews, K. Ehwald, G. Fischer, A. Fox, T. Grabolla, U. Haak, W. Hoppner, F. Korndorfer, B. Kuck, S. Marschmeyer, H. Richter, H. Rucker, P. Schley, D. Schmidt, R. Scholz, B. Senapati, B. Tillack, W. Winkler, D. Wolansky, C. Wolf, H. Wulf, Y. Yamamoto, P. Zaumseil
{"title":"A modular, low-cost SiGe:C BiCMOS process featuring high-f/sub T/ and high BV/sub CEO/ transistors","authors":"D. Knoll, B. Heinemann, R. Barth, K. Blum, J. Borngraber, J. Drews, K. Ehwald, G. Fischer, A. Fox, T. Grabolla, U. Haak, W. Hoppner, F. Korndorfer, B. Kuck, S. Marschmeyer, H. Richter, H. Rucker, P. Schley, D. Schmidt, R. Scholz, B. Senapati, B. Tillack, W. Winkler, D. Wolansky, C. Wolf, H. Wulf, Y. Yamamoto, P. Zaumseil","doi":"10.1109/BIPOL.2004.1365790","DOIUrl":null,"url":null,"abstract":"We demonstrate a BiCMOS process which uses only 22 mask steps to fabricate four types of SiGe:C HBTs, in combination with a triple-well, 2.5V CMOS core and a full menu of passive elements. Key process feature is a 2-mask HBT module. We show that transistors with peak fT values ranging from 3OGHz (@ 7V BV,) up to 130GHz (@ 2.1V BVczo) can he fabricated with this low-cost module. Among the passives are varactors, polysilicon resistors, and a 2fF/pmz MIMsapacitor. Five layers of AI are available, including 2pm and 3pm thick upper layers. SOC ability of the process is demonstrated by a 1MSRAM yield of typically 70%.","PeriodicalId":447762,"journal":{"name":"Bipolar/BiCMOS Circuits and Technology, 2004. Proceedings of the 2004 Meeting","volume":"13 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2004-12-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"18","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Bipolar/BiCMOS Circuits and Technology, 2004. Proceedings of the 2004 Meeting","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/BIPOL.2004.1365790","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 18
Abstract
We demonstrate a BiCMOS process which uses only 22 mask steps to fabricate four types of SiGe:C HBTs, in combination with a triple-well, 2.5V CMOS core and a full menu of passive elements. Key process feature is a 2-mask HBT module. We show that transistors with peak fT values ranging from 3OGHz (@ 7V BV,) up to 130GHz (@ 2.1V BVczo) can he fabricated with this low-cost module. Among the passives are varactors, polysilicon resistors, and a 2fF/pmz MIMsapacitor. Five layers of AI are available, including 2pm and 3pm thick upper layers. SOC ability of the process is demonstrated by a 1MSRAM yield of typically 70%.
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