New OPBHWICAP Interface for Realtime Partial Reconfiguration of FPGA

Abstract

We propose in this paper, a timing analysis of dynamic partial reconfiguration (PR) applied to a NoC (Network on Chip) structure inside a FPGA. In the context of a SDR (Software Defined Radio) example, PR is used to dynamically reconfigure a baseband processing block of a 4G telecommunication chain running in real-time (data rates up to 100 Mbps). The results presented show the validity of our methodology for PR management regarding the timing performances obtained in a real implementation. PR timing is a key point to make SDR approach realistic. These results show that using PR, FPGAs combine the flexibility of SW (software) and the processing power of HW (hardware). This makes PR a tremendous enabling technology for SDR. These results are based on a new IP managing the ICAP component that allows a gain in time of a rate of 124 comparing to the provided OPBHWICAP. Moreover, we have integrated a methodology which can reduce significantly the bitstream size and consequently the reconfiguration duration. The results presented in this paper show that PR reconfiguration time can go downto a few tens of microseconds. This makes PR really attractive for SDR design or any other highly demanding real-time applications.