Design of low power CMOS low noise amplifier using current reuse technique

Abstract

This paper presents a new LNA architecture comprise current reuse topology. The design is carried out in BSNIM3 180 nm CMOS technology. The proposed LNA consumes less power of 12.49 mW as compared to other existing architectures, while providing better gain (16.78 dB) and low NF i.e. less than 5 dB over the frequency range of 3 to 10 GHz. The design offers power gain (S21) of 7.5 dB and input return loss (S11) of -14 dB. All simulations are performed by using EDA Tanner T-Spice and ADS 2011.10 tools.