{"title":"A Transient-Enhanced Capacitorless LDO Regulator with improved Error Amplifier","authors":"S. Alapati, P. SrihariRao, K. Prasad, S. Dixit","doi":"10.1109/ISVLSI.2014.28","DOIUrl":null,"url":null,"abstract":"This paper presents a modified folded cascode error amplifier of low dropout (LDO) regulator and a slew-rate enhancement circuit to minimize compensation capacitance and improve transient response. The proposed error amplifier eliminates the tradeoffs between small and large slew-rate that is imposed by the tail-current in conventional error amplifier design. The design is implemented in a standard UMC 0.18 ìm standard CMOS process. Simulation results show that, the LDO regulator consumes a quiescent current of 49.64μA only with a total power consumption of .079mW. It regulates the output voltage at 1.4v from 1.6-1.8v supply. The overshoot/undershoot in the output voltage under the extreme load transients are 220.7mV/280.26mV for load current range of 0 to 100mA. The line regulation is 1.244mV/V at 1.8V, load regulation is 40.6mV/A. This circuit finds its beneficial behavior for chip-level power management units requiring high-area efficiency as compensation capacitors are avoided.","PeriodicalId":405755,"journal":{"name":"2014 IEEE Computer Society Annual Symposium on VLSI","volume":"44 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2014-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2014 IEEE Computer Society Annual Symposium on VLSI","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISVLSI.2014.28","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 3
Abstract
This paper presents a modified folded cascode error amplifier of low dropout (LDO) regulator and a slew-rate enhancement circuit to minimize compensation capacitance and improve transient response. The proposed error amplifier eliminates the tradeoffs between small and large slew-rate that is imposed by the tail-current in conventional error amplifier design. The design is implemented in a standard UMC 0.18 ìm standard CMOS process. Simulation results show that, the LDO regulator consumes a quiescent current of 49.64μA only with a total power consumption of .079mW. It regulates the output voltage at 1.4v from 1.6-1.8v supply. The overshoot/undershoot in the output voltage under the extreme load transients are 220.7mV/280.26mV for load current range of 0 to 100mA. The line regulation is 1.244mV/V at 1.8V, load regulation is 40.6mV/A. This circuit finds its beneficial behavior for chip-level power management units requiring high-area efficiency as compensation capacitors are avoided.
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