Drain current model for SOI TFET considering source and drain side tunneling

Abstract

In this paper, we have developed a 2-D model for the DC drain current of a tunneling field-effect transistor (TFET) considering the source and the drain depletion regions. Analytical expressions are derived for the surface potential, electric field and the band-to-band generation rate. The drain current is obtained by numerically integrating the generation rate across the entire device. The model is able to predict the ambipolar current as well as the effects of drain voltage in the saturation region. The model uses a semi-empirical approach to capture the transition between the linear and the saturation regions, which gives infinitely differentiable transfer characteristics. This model includes the effects of drain voltage, gate metal work function, oxide thickness, and silicon film thickness. The model is also shown to be scalable down to a channel length of 20 nm. The accuracy of the model is confirmed by a comparison with 2-D numerical simulations.