Row-by-row dynamic source-line voltage control (RRDSV) scheme for two orders of magnitude leakage current reduction of sub-1-V-V/sub DD/ SRAM's

Abstract

A new row-by-row dynamic source-line voltage control (RRDSV) scheme is proposed to reduce the active leakage as well as the stand-by leakage in SRAM. By dynamically controlling the source-line voltage of cells row by row, the cell leakage through inactive cells can be reduced by two orders of magnitude. Moreover, the bit-line leakage through pass transistors can be completely cut off. This leakage reduction is caused from the cooperation of reverse body-to-source biasing and drain induced barrier lowering (DIBL) effects. A test chip has been fabricated using 0.18-/spl mu/m triple-well CMOS technology to verify the data retention capability of this RRDSV scheme. The minimum retention voltage in the RRDSV is measured to be reduced by more than 60 mV, when shielding metal is inserted to protect the memory cell nodes from bit-line coupling noise. It can reduce the leakage by another 50% in addition to the reduction by two orders of magnitude.