Implementation of a 4-Parallel 128-Point Radix-8 FFT Processor via Folding Transformation

Abstract

This work describes the design and implementation of a 4-parallel 128-point pipelined architecture for the fast Fourier transform (FFT) based on the radix-8 butterfly element using folding transformation and registers minimization techniques. In addition, different optimization stages are obtained by applying multiple optimization techniques, including Canonical Signed Digit (CSD) multipliers, quantization, and pipelining. The final result is a high-speed FFT architecture (up to 1.2GS/s) with a reduced area, power consumption, and latency. Finally, this architecture will be implemented in an open-source FreePDK45 of 45 nm CMOS technology.