Comparative Study of Hardware Accelerated Convolution Neural Network on PYNQ Board

Abstract

In recent years convolutional neural networks (CNNs) have been remarkably used in many applications, and they are the heart of many intelligent systems. The advancements in both new electronic design automation (EDA) tools and in new hardware development boards such as Python Productivity for Zynq (PYNQ) have significantly decreased the development time of CNNs. However, the short time-to-market is at the cost of implementation area, performance and power consumption. Over the last period, CNNs’ energy consumption needs have skyrocketed dramatically. Thus, In this work, the authors conduct a comprehensive study on the power consumption of hardware accelerated CNN whether implemented using new EDAs High Level Synthesis (HLS) or the basic design abstraction of Register Transfer Level (RTL). Both methods are implemented on modern development boards from Xilinx (as PYNQ). Modern EDAs flow such as HLS does not represent the best environment for a good power consumption. The power consumption of the HLS implementation is six times more power than the RTL one. It is concluded that the new EDAs method have a deficiency to deliver highly efficient CNNs but it has the ability to deliver sufficient results within a very short period of time.