{"title":"A fully integrated switched-capacitor DC-DC converter with dual output for low power application","authors":"HeungJun Jeon, Yong-Bin Kim","doi":"10.1145/2206781.2206803","DOIUrl":null,"url":null,"abstract":"This paper presents a fully integrated on-chip switched-capacitor (SC) DC-DC converter that supports two regulated power supply voltages of 2.2V and 3.2V from 5V input supply and delivers the maximum load currents up to 8mA at both of the outputs. The entire converter system uses two 2-to-1 converter blocks. The upper output voltage (3.2V) is generated from the 2-to-1_up converter by means of averaging the 5V input and the generated lower output voltage (2.2V), which is generated from 2-to-1_dw converter. Since 2-to-1_up converter is less sensitive to the bottom-plate parasitic capacitance loss, they are implemented with MOS capacitors, which show higher capacitance density (2.7fF/μm2, α=6.5%) than MIM capacitors (1fF/μm2, α=2.5%) while they have bigger bottom-plate parasitic capacitance ratio (α). The proposed implementation saves the area and quiescent currents for the control blocks since each block shares required analog and digital control blocks. The proposed converter is designed using high-voltage 0.35μm BCDMOS technology. Both output voltages are regulated by means of pulse frequency modulation (PFM) technique using 18-bit shift registers and digitally controlled oscillators (DCOs). Over the wide output power ranges from 5.4mW to 43.2mW, the converter achieves the average efficiency of 70.0% and the peak efficiency of 71.4%. 10-phase interleaving technique enables the output voltage ripples of the both outputs less than 1% (<40mV) of the output voltages when 400pF of output buffer capacitors are used for both outputs.","PeriodicalId":272619,"journal":{"name":"ACM Great Lakes Symposium on VLSI","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2012-05-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"10","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"ACM Great Lakes Symposium on VLSI","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1145/2206781.2206803","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 10
Abstract
This paper presents a fully integrated on-chip switched-capacitor (SC) DC-DC converter that supports two regulated power supply voltages of 2.2V and 3.2V from 5V input supply and delivers the maximum load currents up to 8mA at both of the outputs. The entire converter system uses two 2-to-1 converter blocks. The upper output voltage (3.2V) is generated from the 2-to-1_up converter by means of averaging the 5V input and the generated lower output voltage (2.2V), which is generated from 2-to-1_dw converter. Since 2-to-1_up converter is less sensitive to the bottom-plate parasitic capacitance loss, they are implemented with MOS capacitors, which show higher capacitance density (2.7fF/μm2, α=6.5%) than MIM capacitors (1fF/μm2, α=2.5%) while they have bigger bottom-plate parasitic capacitance ratio (α). The proposed implementation saves the area and quiescent currents for the control blocks since each block shares required analog and digital control blocks. The proposed converter is designed using high-voltage 0.35μm BCDMOS technology. Both output voltages are regulated by means of pulse frequency modulation (PFM) technique using 18-bit shift registers and digitally controlled oscillators (DCOs). Over the wide output power ranges from 5.4mW to 43.2mW, the converter achieves the average efficiency of 70.0% and the peak efficiency of 71.4%. 10-phase interleaving technique enables the output voltage ripples of the both outputs less than 1% (<40mV) of the output voltages when 400pF of output buffer capacitors are used for both outputs.