Hardware Support for Combined Interval and Floating Point Multiplication

Abstract

This paper presents the design and implementation of a combined, interval and conventional floating point multiplier, which operates with IEEE 754 numbers. The proposed unit consists of a floating point multiplier - which computes several results of the same operation (rounded differently) - and of two floating point comparator circuits. This architecture implements an algorithm that is suitable for pipelined structures. Furthermore, the two floating point comparators can be used for interval hull and intersection, two of the most frequent interval operations. The cost overhead of the proposed unit is 40% with respect to a conventional floating point multiplier. The performance of the floating point multiplication on the proposed architecture is the same as of a conventional floating point multiplier, whereas the performance of an interval multiplication is almost half-an outstanding result for such a demanding operation.