Filipe Araújo, Miguel D. Fernandes, J. Pinto, L. Oliveira, J. Oliveira
{"title":"Wideband CMOS RF front-end receiver with integrated filtering","authors":"Filipe Araújo, Miguel D. Fernandes, J. Pinto, L. Oliveira, J. Oliveira","doi":"10.1109/MIXDES.2015.7208552","DOIUrl":null,"url":null,"abstract":"A wideband CMOS receiver front-end for radio applications operating between 300 MHz and 900 MHz is presented. In order to obtain channel selection with image-rejection and out-of-band interferers attenuation, both low-noise amplifier (LNA) and mixer incorporate a N-Path signal processing technique. The effectiveness of this N-Path filtering is investigated by comparing distinct combinations of clock phases and respective duty cycle. Using a standard 130 nm CMOS technology and a supply voltage of 1.2 V, it was possible to obtain a voltage gain greater than 28 dB, a noise figure (NF) lower than 6.05 dB and IIP3 > -1.54 dBm.","PeriodicalId":188240,"journal":{"name":"2015 22nd International Conference Mixed Design of Integrated Circuits & Systems (MIXDES)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2015-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2015 22nd International Conference Mixed Design of Integrated Circuits & Systems (MIXDES)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/MIXDES.2015.7208552","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2
Abstract
A wideband CMOS receiver front-end for radio applications operating between 300 MHz and 900 MHz is presented. In order to obtain channel selection with image-rejection and out-of-band interferers attenuation, both low-noise amplifier (LNA) and mixer incorporate a N-Path signal processing technique. The effectiveness of this N-Path filtering is investigated by comparing distinct combinations of clock phases and respective duty cycle. Using a standard 130 nm CMOS technology and a supply voltage of 1.2 V, it was possible to obtain a voltage gain greater than 28 dB, a noise figure (NF) lower than 6.05 dB and IIP3 > -1.54 dBm.