Design of Multicore Dataflow DSPs with Different Loop Iteration Mechanisms

Abstract

FPGA technology and dataflow approach offer the potential for high performance in many applications including IoT-connected consumer electronics and so on. A dataflow approach inherently brings the potential for parallel execution of programs. In our laboratory, we have developed a ring interconnected multicore dataflow DSP called LSC-Based DSP. In this work, we design LSC-Based DSPs with two different kinds of loop iteration mechanisms. We implement these our DSPs on an FPGA and measure the execution time of a test program.