Low power Optimum Design of BCD Adder in Reversible Logic

Abstract

Reversible logic has captured significant attention in recent time as reducing power consumption by recovering bit loss from its unique input-output mapping. This paper presents a compact $n -$digit BCD adder where a low cost reversible ODU gate is proposed. Theoretical explanations certify the novelty of the proposed design. Comparing with previous works the proposed design shows significant improvement in all performance metrics compared to the best existing BCD adder, as an example, the proposed 512-bit reversible BCD adder improves 38.46%, 47.83%, 70.60% and 63.64% in terms of number of gates, garbage outputs, quantum cost and delay compared with the existing best design.