Development synthesizer of stable high-frequency signal

Abstract

Variants of the frequency synthesizer capable multiply and divide the input frequency were analyzed. To multiply the frequency of synthesizer a phase locked loop (PLL) was used. Variants of voltage controlled oscillator (VCO) for the PLL, and low-pass filter (LPF) were considered, justifying the choice of used schemes. Synchronization block was added to developed synthesizer for redundancy possibility. Developed synthesizer circuit was simulated at different temperatures and voltages. Simulations have shown that the PLL loop working in the multiplication mode converges to a required frequency and covers the predetermined frequency under all specified operating conditions. In frequency division mode the synchronization also runs successfully.