{"title":"A 40MHz-BW 35fJ/step-FoM nonlinearity-cancelling two-step ADC with dual-input VCO-based quantizer","authors":"Peng Zhu, Xinpeng Xing, G. Gielen","doi":"10.1109/ESSCIRC.2014.6942022","DOIUrl":null,"url":null,"abstract":"This paper presents a nonlinearity cancellation technique in a closed-loop two-step VCO-based ADC, where the VCO's distortion is substantially mitigated in a robust manner. A dual-input VCO-based quantizer topology is proposed to realize a low-power multi-input adder, with no penalty in terms of nonlinearity. Fabricated in a 40nm CMOS process, the prototype two-step 12-bit ADC achieves 68.7dB/66.8dB SNR/SNDR with a 40MHz bandwidth and consumes only 4.98mW. This corresponds to an excellent FoM of 35fJ/step.","PeriodicalId":202377,"journal":{"name":"ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2014-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"13","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ESSCIRC.2014.6942022","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 13
Abstract
This paper presents a nonlinearity cancellation technique in a closed-loop two-step VCO-based ADC, where the VCO's distortion is substantially mitigated in a robust manner. A dual-input VCO-based quantizer topology is proposed to realize a low-power multi-input adder, with no penalty in terms of nonlinearity. Fabricated in a 40nm CMOS process, the prototype two-step 12-bit ADC achieves 68.7dB/66.8dB SNR/SNDR with a 40MHz bandwidth and consumes only 4.98mW. This corresponds to an excellent FoM of 35fJ/step.
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