Hardware Fault Free Simulation for SOC

V. Hahanov, M. Kaminska, W. Ghribi, A. Hahanova
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Abstract

In the paper structure functional multi-valued hardware model of digital device is offered; two-circuits structure functional multi-valued hardware model of digital device for multiple input patterns co-simulation and multiple increasing of performance transient analysis in sequential structures is proposed; automatic model of HDL-code transmission process to data structure for digital system on chip analysis and verification with hardware is proposed.
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SOC硬件无故障仿真
本文给出了数字器件的结构功能多值硬件模型;针对时序结构的多输入模式联合仿真和多增益性能瞬态分析,提出了数字器件的双电路结构功能多值硬件模型;提出了用于数字系统片上分析和硬件验证的hdl码传输到数据结构的自动模型。
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