{"title":"A fast multi-operand multiplication scheme","authors":"Hideaki Kobayashi","doi":"10.1109/ARITH.1981.6159279","DOIUrl":null,"url":null,"abstract":"Recent developments in integrated circuit technology have made efficient schemes for computer arithmetic possible. This paper discusses a generation-summation scheme for fast multi-operand multiplication. Synthesis of three-operand multipliers utilizing a single type of standard LSI device is also discussed.","PeriodicalId":169426,"journal":{"name":"1981 IEEE 5th Symposium on Computer Arithmetic (ARITH)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1981-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"1981 IEEE 5th Symposium on Computer Arithmetic (ARITH)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ARITH.1981.6159279","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 5
Abstract
Recent developments in integrated circuit technology have made efficient schemes for computer arithmetic possible. This paper discusses a generation-summation scheme for fast multi-operand multiplication. Synthesis of three-operand multipliers utilizing a single type of standard LSI device is also discussed.
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