An Efficient Architecture for Golay Code Encoder

Abstract

The Golay codes are widely used Error Correction Codes (ECCs) that are used to recognize and correct errors in digital systems. This paper proposes an efficient architecture for hardware implementation of Golay code encoder. The proposed architecture has three important units: 1) data unit, 2) control unit and 3) conversion unit. These units are carefully designed such that the developed architecture can work for a message with ‘0’ and ‘1’ Most Significant (MS) bits. The performance of the developed encoder architecture is verified using FPGA devices. The results demonstrate that the developed encoder architecture provides a promising advantage compared to other encoder architectures for Golay codes.